Notes 1 -CMOS Fundamentals

Hello Electro Geeks,

Welcome back!!!

To learn more everyday it is necessary to read and gain more knowledge. This post is about my notes which is frequently asked upon. In this post I would like to familiarize you regarding the basics of the PnR flow, what components are used, why those are used and fundamentals of these components and theory.

CMOS FUNDAMENTALS

In the design of the chip we generally use standard cells NAND gates, in MOS logic gate.

There are 2 universal gates which can replicate each logic equation : NAND and NOR gates.
We use NAND gate due to its area occupancy is less than the NOR gate, as we know the PMOS takes more area than the NMOS due to its lower conductivity. NAND transition time is also less than NOR.
There are many devices which has been out after the ENIAC was the invention of a transistor :
BJT- Bipolar Junction Transistor. But due to high power consumption it was disregarded.

MOS - Metal Oxide Semiconductor device

MOS characteristics

• It is a device used as a switch and amplifier. Switch -when it in linear -[1] and cutoff region -[0], Amplifier - in saturation region
• Through MOS all digital gates can be designed.
• Usually we go with CMOS -Complementary MOS , having PMOS and NMOS.

Why we choose CMOS over BJT?

• In designing we take care of 3 factors optimization : Power, Performance, Area. BJT qualifies in Performance and area, but fails in power optimization because it is a current controlled device intakes huge power consumption run a gate which puts an upper limit to the number of gate used.
• Whereas MOS is a voltage controlled device gives :huge integration densities and less power consumption compared to only-pmos and only nmos, CMOS optimize all the 3 factors.
• Number of terminals are 4 : Source, Gate, Drain, Substrate/body

Pic 1

• Mos is a gate controlled terminal, when gate voltage of an nmos is greater than the threshold voltage , input is transferred to out. Hence, gate controls whether the device is ON or OFF
• gate ON means : Source - gives carriers and drain collects carriers. Connectivity is established and current flows.
• Source and drain are interchangable in MOS.

Pic 2

Power Dissipation

Pic 3

NMOS

• Vth(Threshold voltage)=V(gate voltage) "device just turned ON"
• NMOS is pull down network 
• therefore, Vb(Voltage of body) = 0
• Vb directly proportional to Vth

Condition: 

• If Vth is low device is much faster and has maximum performance.
• If Vth increases Static power dissipation decreases and goes into power saver mode, gives slower device performance which is not required.

Pic 4

PMOS

• Works when Vg < 0
• Vout =1 when Vg=0
• Here Vb is inversely proportional to Vth
• Hence Vb should be at a higher potential to keep Vth  lower.

Body Electric fields

• There are 2 E-fields in the body vertical and horizontal
• Vertical : provides channel formation
• Horizontal : provides current flow

Voltage is directly proportional to the technology

• Because as technology decreases distance between the 2 port drain and source decreases.
• As you know E= V/d
• As d decreases Electric field increases, if V is kept same and it is sufficient to burn the device.
• So the solution is to reduce the Voltage whilst decreasing the distance od source and drain hence technology.

Parameters to optimize are:

1. Package 
2. Cost
3. Performance
4. Reliability

MOS power dissipation affects the above parameters hence this step of reducing power dissipation is most important.

MOS power dissipation

1. Static Power dissipation
2. Dynamic power dissipation
3. Leakage power

MOS behaves as a resistor when it is ON it has different intrinsic capacitance and inductance component. Current flowing through MOS contributes to power dissipation.

• As the technology node decreases, Vth decreases, which inturn increases static power dissipation.
• Subthreshold conduction increases.
• Degrades the noise margin, giving logic voltages no longer are equal to supply rails.
• Leakage current increase static power dissipation.
• Dynamic power dissipation is not affected by it.
• Trade - off is needed for supply and the threshold voltage for each operating device.
• Least static power can be achieved by put the non-active device in stand by mode.
• Designing mutually exclusive pull-up and pull-down network to eliminate static power dissipation.
• Using Psedo -NMOS and DCVSL logic can reduce static power dissipation and reduce area requirement of the logic.

Static Power Dissipation

• Battery drain out
• MOS pn junction is formed which in intrinsic diode formation in reverse bias cause leakage current and power dissipation.

Dynamic Power Dissipation

• Usually Dynamic Power Dissipation > Static Power Dissipation
• Caused by charging and discharging of capacitor
• 1/2 C(Vdd)^2
• Dynamic Power Dissipation decreases as Vdd decreases.

Short circuit power (Internal power)

• When switching 0-1 or 1-0 a time exist when both nmos and pmos are ON
• Power consumed is the internal power and current finds a short with Vdd and gnd with 2 resistor components dissipates power.

CMOS

• Due to slow rise time, there occurs charging and discharging of parasitic capacitance present at gate.
• source and drain forms the 2 plate of the capacitor and dielectric is formed by the gate with SiO2 poly oxide layer.
• As gate area increases power dissipation decreases.

When Technology decreases device becomes faster, area decreases causing increase in dynamic and static power dissipation.

• Short channel length effects
• less noise margin
• electro migration causes channel break

ASIC/ SoC PHYSICAL DESIGN FLOW

SEMICUSTOM FLOW

3 major tools used are :

• ICC for PnR place n route by Synopses
• Invance by Cadence
• Blast by Mento graphics