Notes 3 Floorplan

 Floorplan

What is floorplan?
Floor plan is planning your floor to get optimised congetion and meet timing requirement with adequate power supply to all pins of all instances.

• Planning your floor - floor is die
• Die Size Estimation
• IO and macro placement
• Channel length estimation
• Planning power distribution

Steps

• Die size estimation - The die is made out of a wafer, this size estimation is done to put maximum gates as the technology follows Moore's law.
• IO port placement - The IO port placement is done on the die to core boundary.
• Macro placement - According to data - lines connectivity and hierarchy the macros are placed, which appropriate channel width to accommodate all the connections and placed in such a way to reduce wire length.
• Row creation - Rows are created to place the standard cells around the macros are placed and fixed. 
• Power routing/ Power planning - Then power grids are provided to each instances according to their requirement.

Floorplan can be judged by the Quality of Result (QoR) parameters are set to consider a floorplan to be optimal is the trade-off between

1. Power consumed - Due to IR, electromigration, Antenna effects, wire length
2. Performance at a particular frequency - timing is met, critical nets are met are checked
3. Area(congestion) - reduce usage of buffers and spare cells to as minimum as possible.

Floorplan is important in ASIC/Soc design

Procedure to perform floorplan

1. Calculate the die size- check whether it can accomodate all the gate level area + additional area for blocakages, etc.)

Challenges

1. Routing (Congestion of netlist (functional element))
2. Utilisation ratio should be 70% = Core Area/Die Area

• IO and macro placement 
• Channel length Estimation - for interconnection of pins of instances
• Power planning distribution- check IR drop which result in Voltage reduction, hence delay which impacts performance, impacts other elements not getting enough power. All metals has IR drop due to intrinsic resistance of metal with robust power grid we can reduce the impact of IR drop

Floorplan types by design limitation

• Based on outer boundary of die

1. Core limited design : The chip size is limited by the core size
2. Pad limited design : The chip size is limited by the pad area in the design. 

Latency - amount of time for clock to reach from one point to another point.

For clock port placement

1. Reduce latency

For data port placement

Macro placement

1. Same hierarchy macros are kept together which results in optimization of power, buffer, timing

Channel Length estimation

DRC violation- when the design violates the technology file rules then it is difficult to implement fabrication and further processing impacting signal integrity.

1. timing transition is met maximum fanout is met
2. Physical constraints - minimum spacing, minimum width are met

Physical constraints - DRC

1. Wire shorted
2. Physical constraint violated wire open

As the metal layers increases the thickness increases 

Area = thickness x width;

Area increases which is inversely proportional to Resistance

Therefore, Power is directly proportional to Resistance, hence it decreases.

PLL - is used in the design due to its useful characters

1. minimizes the clock edges
2. defined phase relation
3. less gitter in edges of clock
4. due to feedback mechanism

IO pads in a chip-

1. EHD protection (protection against hand warmth)
2. Signal Integrity

Poly is always present in the vertical. So macros are placed only horizontally.

I/O Port Placement

• Assigning Physical location for the I/O ports present in the design
• Typical I/O port location format:

1. TCL file
2. DEF
3. Excel sheet

Core Area

• Core Area is defined for the placement of standard cells and hard macros.
• Standard cell rows are created in the core area for standard cell placement.
• Height of such row is Cell Row Height(CRH).
• Height of Standard Cells is equal to or integral multiple of CRH.
• These Std cell rows could be stacked, abutted, flipped as the technology and design may require.

Macro Placement

• Macro placement is done based on Connectivity information.

1. Macros to IO cells
2. Macro to Macro
3. Macro placement is very critical for congestion and timing
4. Macro placement should result in uniform standard cell area.

• Macro Placement Requires

1. Fly-line Analysis
2. Data-flow Analysis
3. Design Module Hierarchy Analysis
4. Channel length calculation

Types of Macros

• Memories -RAM, ROM
• PLL/DLL
• ADC/DAC
• DSP Cores
• ARM Cores
• Graphics Cores

Macro Placement Guidelines

• Group the macros based on

1. Instance Hierarchy
2. Connectivity(fly-lines)
3. Data-flow Diagram

• Never in middle or center except they are timing critical

Reason :

• Macro's have blockages(routing) upto M5 leading to congestion
• More buffers added due to routing detour
• More delay & power
• IR drop issues

1. Place the macros where no I/O ports
2. place the macros where less number of I/O ports are there
3. To place macros where more I/O ports are present to provide more routing space
4. Provide uniform cell area

Placement blockages

What are they?

• totally or partially block cell placement in an area
• can prevent any cell or particular type of cells from being placed
• helps reduce congestion & timing costs

Benefits :

1. To prevent (or reduce) cell placement in local areas
2. To reduce congestion in local areas

General floor planning guidelines

• Place the macros close to the boundary of the core
• see that macro pins face core side
• group the macros belonging to same logic block
• keep sufficient channels between macros
• may have to control the cell placement around macros
• avoid notches in floorplan

Congestion:

• Design area is divided into regions - called Global Route Cells(GRC)
• Based on technology each GRC has fixed number of tracks in every layer
• Demand tracks - Available Tracks = GRC Overflow
• This overflow situation leads to Routing Congestion

Reasons:

• High Cell Density
• High pin density
• Blockages
• Large Macros Nearby

Solutions :

• Reduce local cell & pin density
• remove unwanted blockages
• review macro placement

Floorplan Qualification : 

• Number I/O ports short
• All macro's in placement grid
• No macro's overlapping
• Do power routing
• No PG nets DRC & LVS violations
• Perform quick placement
• Analyze the results, if not happy continue all the above steps to qualify the floorplan.