Notes 2 Design Inputs

Design Inputs

Parasitic Capacitance

gds - sent to foundary to fabricate chips tsmc is the largest foundary.

ASIC/SoC method

• Front end

1. Developing chip -Architecting chip, VHDL verilog, RTL, verification on netlist, Validation when chip is back.

• Backend

1. pnr
2. post layout STA
3. Physical Verification

AND gate in netlist format

module AND(A,B,Z)

input A,B;

output Z;

assign Z=A&B

end

OR 

module AND (A,B,Z)

input A,B;

output Z;

AND 2x1 i_and (.i0(A),.i1(B),.O(z))

PnR -> Gate to physical level in file format gds tool.

AND gate needs 3 PMOS , 3 NMOS

PnR steps

1. Design Input

• library models creating milky way library
• Timing - Delay when signal is appearing to ICC compiler. Information of every cell of standard cell library.
• Sequential Circuit - f(Zprevious output, present input)
• Combination circuit

sequential element- is a memory element here for simplicity we take D Flip flop it has 1 bit memory storage.

sequential circuit = sequential element + combinational circuit;

Flip -flops are edge triggered - +ve edge triggered and -ve edge triggered. Edge triggered means the ouput arrrives with respect to clock and not with respect to input.

3 timing Arcs are present in the Flip- flop 

1. clock to Q delay
2. Setup time 
3. Hold time

Block Level Implementation- Inputs

• Library models -Timing (LIB), Physical(LEF)
• Technology data (LEF)-metal layers,drc rules
• Design Netlist(.verilog or vhdl)
• Timing constraints(.sdc)
• Block size and shape
• Pins location(Pad location at top level)
• Blockage information- Placement blockage to avoid placement at some areas, routing blockage to avoid routing in some areas
• Power network- Pushdown from top level, build from bottom-up

Block Level implementation -Outputs

• DEF-Design representation with placement and routing
• LEF-Abstracted model of subchip for top level use with pins location/Blockages.
• ILM-Abstracted timing model for top level use
• Spef- RC parameters based on real Routing for each net in design
• Spice netlist- For running LVS
• GDSII- physical data (Binary format) understood by different tools.
• Netlist

Block Level Implementation

• Load all inputs required into implementation tool
• Run sanity checks
• Save design for next step

Design Import - Sanity Checks

• Library Checks
• Netlist Checks
• SDC Checks
• Netlist vs SDC checks

Design Import - Sanity Checks

• Library Checks - 

1. All cells have timing data(.libs for all cells)
2. All cells have Physical data(.LEF for all cells)

• Netlist Checks

1. Floating nets/pins
2. Multi driven nets
3. Black- boxed modules
4. Combinational loops

Design Import - Sanity Checks

• SDC checks

1. Clocks reaching all clock pins of flops
2. Ports missing input/output delays
3. Ports missing slew/Load constraints
4. Multiple clocks driving same register

• Netlist vs. SDC checks

1. Pre-Layout Timing

LEF-Library Exchange Format provides 2 views - FRAM view and LEF view

LEF is mainly used for showing physical information of cell

Physical view -also has 2 views 1. Abstract view - only required information 2. Layout view - circuit fabrication on silicon, all information is present.

Netlist contains

1. Number of standard cell, components,logically connected
2. memory analog input
3. their connection

Timing Constrainst

1. Clock information - ICC tool to optimise timing requirement met by clock - setup and hold
2. Environment information - load, interaction with others, signal strength
3. IO delay information- delay in input and output ports to send to others modules without deterioration
4. Block size and shape